Winmaxsystemscorporation
Physical Design Engineer
San Jose, CA, United States
Sponsorship not specifiedDetected 3518 days ago
C++CadenceVerilogElectrical EngineeringCommunication
About the role
- All your information will be kept confidential according to EEO guidelines.
Responsibilities
- Physical Design Engineer
Requirements
- Min. years overall: 7+ years of industrial experience after BS/MS degree.
Nice to have
- The qualified candidate will possess the following:
- Candidates will be required to be familiar with industry CAD methodologies and guidelines using primarily Synopsys EDA tools for design and timing closure.
- Hands on experience with Synopsys ICCII, PrimeTime, Design Compiler, MRV, Cadence Conformal.
- Understanding of hardware description language such as SystemVerilog is a plus.
- Candidate should possess a strong understanding of static timing analysis, clock/power distribution and analysis, RC Extraction and correlation, place and route, circuit design and analysis.
- Hands on experience on timing closure.
- Scripting and programming experience using several of the following:
- Perl, C, C++, TCL, Scheme, Skill, and Make is a plus.
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