Nuvacore

Nuvacore

CPU DFT Engineer

Austin, TX · Senior · Full-time

Sponsorship not specified$140k-$250kDetected 44 days ago
PythonVerilogCommunication

Stay score

odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

H-1B wage level

the lottery is wage-weighted — each level is one more entry

Level I · 1×
Level I$116,9581 entry
Level II$145,5582 entries
Level III$174,1793 entries
Level IV$202,7794 entries

$5,558 more — $145,558 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.

Based on the DOL prevailing wage for this occupation and worksite, a base salary of $145,558 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Computer Hardware Engineers" for prevailing-wage purposes.

DOL prevailing wage, 2026-27 wage year · Computer Hardware Engineers (17-2061) · Austin-Round Rock-San Marcos, TX. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.

Employer immigration record

from this employer's Department of Labor filings

Files H-1B transfers

8 transfer filings in the last year, covering 8 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • As a CPU DFT Engineer, you will participate in the following areas:
  • Completing DFT architecture specifications
  • Review and integrate third party IPs into DFT architecture

Responsibilities

  • Defining and implementing area and power efficient DFT architecture while collaborating with design, STA and PD
  • Develop scan and BIST insertion flows, implement DFT registers in design blocks
  • Generate test content for silicon bringup, and support silicon bringup activities including yield analysis
  • Using DFT features to support system debug

Requirements

  • Scan or MBIST with industry standard EDA tools, or experience with DFT verification flows
  • Experience with Verilog RTL and gate level netlists, including running and debugging simulations
  • Strong communication skills and ability to work with cross functional teams

Skills

  • Leveraging AI tools to accelerate DFT work flows

Compensation

  • $140k-$250k

This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.