Nuvacore

Nuvacore

CPU Custom Library Cell Design (IC)

Austin, TX · Senior · Full-time

Sponsorship not specified$140k-$250kDetected 34 days ago
Agentic AIElectrical EngineeringCommunicationCollaboration

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odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

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from this employer's Department of Labor filings

Files H-1B transfers

8 transfer filings in the last year, covering 8 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • As a Custom Library Circuit Engineer, you will participate in the following:

Responsibilities

  • Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads.
  • As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.
  • Design and characterize library cells including flip-flops, clock-gating cells, level shifters, and special purpose AOI cells to optimize PPA at advanced process nodes.
  • Own end-to-end library IP closure: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization
  • Partner with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark new process technology, validate IP on test chips, and co-optimize cells for downstream design PPA.

Requirements

  • Hold a BS or MS degree with (ideally) 12+ years of experience in standard cell and/or custom memory circuit design.
  • Hands-on transistor-level design experience with static circuits and state-retaining elements (latches, flops), as well as custom logic gates at advanced CMOS nodes.
  • Experience translating PDK device characteristics into circuit decisions.
  • Proven PPA-focused execution for standard cells, including architecture trade-offs, critical-path modeling, full-cut analysis, and Monte Carlo variation studies.
  • Experience using Agentic AI tools for productivity and automation.

Compensation

  • $140k-$250k

This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.