Etchedai

Front-End Power Engineer

Cupertino, CA

Sponsorship not specifiedDetected 118 days ago

PythonNLPCadenceVerilogResearch

About the role

We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Optimize RTL designs to boost power efficiency while meeting performance and area objectives.
Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling.
Conduct power estimation and evaluate PPA trade-offs for both new and existing design features.
Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases.
Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions.
Experience in RTL development using Verilog/SystemVerilog, with a focus on low-power RTL design and optimization for complex digital systems.
Relocation support for those moving to Cupertino
We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware.
Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

In-depth knowledge and experience in implementing low-power techniques like clock gating, power gating, and dynamic voltage/frequency scaling (DVFS).
Familiarity with synthesis and place-and-route processes with an emphasis on optimizing for power.
You may be a good fit if you have
Strong candidates may also have experience with

We are a fully in-person team in Cupertino, and greatly value engineering skills.

This listing is sourced directly from Etchedai's careers page and normalized into a canonical job model.