NXP Semiconductors
Principal DFT Engineer
Austin (Oakhill, Office) · Principal
Sponsorship not specifiedDetected 30 days ago
iOSVHDLVerilogSensorsMicrosoft Office
About the role
- MMEDE BU brings the technology and ecosystem relationships for next gen automotive Processing, Edge Processing & Radar Processing products.
- More information about NXP in the United States...
- In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6692
Responsibilities
- Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.
- The engineer should be well versed in Digital Design Concept, preferably having subject knowledge on Verilog/VHDL RTL coding.
- You will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE).
Requirements
- DFT engineer with 5 + years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
- The candidate should preferably have experience in any one of the following areas.
Benefits
- Analyzing ATPG reports on coverage & devise mechanism to improve coverage & generating patterns for ATE.
- Scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
Equal opportunity
- NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.
Apply directly at NXP Semiconductors →Create a free account for alerts like thisView NXP Semiconductors immigration profile
This listing is sourced directly from NXP Semiconductors's careers page and normalized into a canonical job model.