Neuralink
Analog IC Layout Engineer
South San Francisco, California, United States · Mid · Contract
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~30% per draw at Level II). Good if you win; have a cap-exempt backup on your list.
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Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($83,000) is below the Level I prevailing wage of $106,038. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $133,973 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electrical Engineers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electrical Engineers (17-2071) · San Francisco-Oakland-Fremont, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Crafting state-of-the-art layouts for mixed-signal and analog circuits
- Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
- Physical verification of custom IC mask layouts (LVS, DRC, ERC)
Responsibilities
- The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems.
- You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team.
Requirements
- Bachelor of Science in Computer Engineering or related field
- 2+ years of experience in analog and mixed-signal IC layout design
- 1+ year experience with FinFET technologies
- Ability to identify the best approach to solving problems
Nice to have
- Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
- Understanding on failure-prone circuit and layout structures
- Experience with analog DFM standards
- Experience with layout P-cell design and implementation
- Experience with layout automation
- Expected Compensation:
- We also believe in aligning our employees' success with the company's long-term growth.
Compensation
- The anticipated base salary for this position is expected to be within the following range.
- Your actual base pay will be determined by your job-related skills, experience, and relevant education or training.
- As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.
- $83,000 - $139,000 USD
Benefits
- Full-time employees are eligible for the following benefits listed below.
- Excellent medical, dental, and vision insurance through a PPO plan
- Commuter benefits
- Equity (RSUs) *Temporary Employees & Interns excluded
- Parental leave *Temporary Employees & Interns excluded
- Flexible time off *Temporary Employees & Interns excluded
Company info
- We are creating devices that enable a bi-directional interface with the brain.
- These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
- We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology.
This listing is sourced directly from Neuralink's careers page and normalized into a canonical job model.