Altera
DFT Design Engineer
San Jose, California, United States
Sponsorship not specified$143k-$207kDetected 30 days ago
FPGAElectrical EngineeringSignal ProcessingLeadership
About the role
- You will also contribute to the development of DFT methodologies and flows to improve pre-silicon and post-silicon validation processes.
Responsibilities
- Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
- Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
- Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
- Partner with test development teams to support silicon bring-up, debug, and production readiness.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 7+ years of industry experience in the following - OR.
- Master's degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of industry experience in the following:
- Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools
- Design automation experience and proficiency in scripting languages such as Perl/TCL
- Applicants must be eligible for any required U.S. export authorizations.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Experience in DFT design and verification at both RTL and gate level.
Nice to have
- Experience with test compression, BIST (MBIST/LBIST), and advanced fault models.
- Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.
- Shift 1 (United States of America)
- San Jose, California, United States
- Posting Statement:
Skills
- Our innovation in programmable logic began in 1983.
- Join us on our journey to becoming the world's #1 FPGA company!
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $142,600 - $206,500 USD
Benefits
- Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.
Company info
- The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.