Astera Labs Inc.

Senior Principal Digital Design Engineer

San Jose, CA · Principal

Sponsorship not specified$205k-$255kDetected 5 days ago

CadenceEmbedded SystemsElectrical EngineeringLeadershipCollaborationMentoring

About the role

Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.
As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.
Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity.

Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
Establish architectural standards and best practices that scale across the design organization
Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
Own accountability for design quality, schedule, and successful production delivery
Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
Work with firmware and software teams to optimize hardware-software interfaces
Mentor and develop junior and senior engineers, elevating team technical capabilities

Bachelor's degree in Electrical Engineering or equivalent
Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
Production experience with advanced CMOS nodes (≤7nm)
Proficiency with Cadence and/or Synopsys digital design flows

Master's degree in Electrical Engineering or related field
Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
Experience leading technical teams or driving cross-functional initiatives in data center environments

Salary range is $205,000 to $255,000 depending on experience, level, and business need.

Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.