Eliyan Corporation

Eliyan Corporation

Digital - ASIC Design Automation & Integration Engineer

Bay Area, Vancouver or Toronto · Senior · Full-time

Sponsorship not specifiedDetected 162 days ago
PythonBashGitCI/CDGitHub ActionsJenkinsLinuxLLMsVerilogElectrical Engineering

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odds of building a lasting career here

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Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

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Files H-1B transfers

3 transfer filings in the last year, covering 3 workers. Median labor-condition decision: 10 days. An employer that already files transfers is one that can take over an existing H-1B.

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About the role

  • Lint / CDC / Synthesis Quality · IP & Chip Integration · AI-Augmented Design Flows · CI/CD for RTL On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON Full-Time - Equity Participation - Comprehensive Benefits ABOUT THE ROLE Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY
  • technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes. We are looking for an engineer who can own the intersection of design quality, automation, and design integration. In this role you will define

Responsibilities

  • Design Quality & Signoff
  • Define and maintain lint, CDC, and synthesis elaboration signoff criteria across all active design programs.
  • Build and own the waiver management system - structured flow with owner attribution, justification, expiration, and audit trail.
  • Collaborate with project design leads to develop and maintain project-specific rule decks, synthesis constraints, and signoff checklists.
  • Own RTL integration of digital IP into PHY and chip-level hierarchies - instantiation, parameterization, hierarchy assembly, and interface consistency across IP boundaries.
  • Build automated integration checks: top-level connectivity, tie-off and floating-input detection, clock and reset connectivity, and interface consistency between IP and SoC.
  • Own IP release packaging and delivery - versioned collateral, dependency tracking, and reproducible builds from a tagged release, with handoff evidence for internal and customer deliveries.
  • Run lint, CDC, RDC, and elaboration at full-chip scope, and drive cross-IP and integration-level findings to closure with the owning designers.
  • Own the Jenkins-based CI pipeline for RTL quality: lint, CDC, RDC, elaboration, synthesis, and STA.
  • Build the dev-to-release promotion pipeline with automated gating, clean-run qualification, and handoff evidence generation.

Requirements

  • Familiarity with Lint/CDC/RDC tools like VC SpyGlass or QuestaLint/CDC.
  • Familiarity with Synthesis tools like Genus or Fusion Compiler.
  • Working knowledge of SystemVerilog and the RTL front-end flow - able to read violations, assess severity, and disposition findings.
  • Proficiency in Python, Tcl, shell scripting, Git, Linux, and Makefiles.

Nice to have

  • Experience with register map automation and IP packaging standards (PeakRDL, SystemRDL, or IP-XACT).
  • Knowledge of UPF and power intent.
  • Knowledge of Static Timing Analysis.
  • Practical experience with LLM APIs or agent frameworks (e.g., Anthropic Claude, OpenAI) applied in a production or team-facing context.
  • Hands-on experience integrating and releasing digital IP - hierarchy assembly, connectivity closure, versioned collateral, and handoff to internal or external consumers.

Company info

  • IP and chip-level integration ownership is scope you can grow into as you ramp - we're looking for someone who wants it.

Visa & Work Authorization

  • Authorization to work in the United States or Canada; visa sponsorship may be considered for exceptional candidates.
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