Altera
Physical Design Engineer
San Jose, California, United States · Mid
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~30% per draw at Level II). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($105,000) is below the Level I prevailing wage of $124,405. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- The pay range below is for Bay Area California only.
Responsibilities
- Other responsibilities of the Physical Design Engineer include but are not limited to:
- Support block-level and/or top-level physical design implementation for FPGA and ASIC-style designs, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
- Work with senior physical design engineers to optimize designs for timing, power, area, congestion, and routability.
- Participate in implementation tasks across the physical design flow, including netlist handoff, constraints setup, synthesis/physical design handoff, and signoff readiness.
- Run and analyze timing, power, congestion, and design rule reports to identify issues and support closure activities.
- Collaborate with RTL, design, DFT, CAD, and verification teams to resolve design and flow issues impacting physical implementation.
- Support static timing analysis (STA), timing closure, and engineering change order (ECO) implementation activities.
- Help debug physical design issues related to setup/hold violations, clocking, congestion, IR drop, or design rule violations.
- Assist with physical verification tasks including DRC/LVS checks and design signoff preparation.
- Develop and maintain scripts and automation to improve physical design productivity and flow efficiency.
Requirements
- Experience with industry-standard physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler, or similar tools.
- Experience reviewing and debugging timing, congestion, area, and power reports.
- Familiarity with physical verification concepts including DRC/LVS and signoff quality checks.
- Strong understanding of digital design fundamentals and CMOS/VLSI concepts.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- Physical design fundamentals including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
- Understanding of static timing analysis (STA), timing constraints, setup/hold concepts, and timing closure methodologies.
- Exposure to scripting or automation using Tcl, Python, Perl, or similar languages.
- Knowledge of semiconductor design flows, from RTL handoff through physical implementation and signoff.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Experience with advanced-node physical design methodologies and low-power implementation concepts.
- Exposure to FPGA, SoC, or high-performance semiconductor product development.
- Familiarity with power planning, IR drop analysis, signal integrity, electromigration (EM) analysis, or physical signoff flows.
- Experience working in Linux/Unix-based development environments.
- Strong problem-solving skills and the ability to work effectively in a collaborative team environment.
- Shift 1 (United States of America)
- San Jose, California, United States
Skills
- About Altera
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $105,000 - $120,000 USD
Company info
- We also offer incentive opportunities that reward employees based on individual and company performance.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.