Ambarella Corp.
Physical Design Engineer
US Headquarters · Full-time
Sponsorship not specified$140k-$156kDetected 32 days ago
PythonNode.jsCadenceVHDLVerilogElectrical EngineeringHardware Design
About the role
- AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.
- The base salary range is $140,000 - $156,000.
- Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Responsibilities
- The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.
Requirements
- 3- 5+ years' experience,
- Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC would be an added advantage.
- Hands-on experience in STA including multi-mode multi-corner analysis and ability to analyze and fix critical timing issues.
Nice to have
- Proven track record of delivering tape-out quality GDSII with silicon success in sub 10 nm is a plus.
Compensation
- The base salary range is $140,000 - $156,000.
- Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Benefits
- AI Vision Processors For Edge Applications
Company info
- The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella's cutting edge low power AI SoC from Netlist to GDSII.
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This listing is sourced directly from Ambarella Corp.'s careers page and normalized into a canonical job model.