Normal Computing
Hardware Engineer, FPGA
New York City
Sponsorship not specified$10k-$100kDetected 6 days ago
PythonC++Full-Stack DevelopmentGitDockerCI/CDMachine LearningAccessibilityProcurementFPGAVHDLVerilogSignal ProcessingResearch
About the role
- Validating conventional silicon is a solved discipline.
- Validating silicon that computes with noise is not, and you will be the one who figures out how.
- Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.
Responsibilities
- bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization.
- selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.
- Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
- Design, implement, and validate high-speed
- Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments.
- Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.
- CI/CD for hardware (GitLab CI, Docker-based build and test).
- RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.
- Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.
Nice to have
- Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).
- Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.
Skills
- Strong board-level bring-up and lab debugging skills on real hardware.
- Verification frameworks like Cocotb or UVM
Compensation
- $10k-$100k
Equal opportunity
- Normal Computing is an Equal Opportunity Employer.
- We celebrate diversity and are committed to creating an inclusive environment for all employees.
- All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
- Accessibility Accommodations
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