Astera Labs Inc.

Technical Chief of Staff for ASIC Engineering

San Jose, CA · Exec

Sponsorship not specified$216k-$300kDetected 5 days ago

PRDsCadenceLeadershipCommunicationProblem Solving

About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
This role is a force-multiplier for Engineering leadership - driving org scale, decision velocity, and execution rigor.
The role is fully in person in San Jose.

What You Will Own
Manage escalations and organizational friction - diagnose root causes, coordinate resolution paths, and ensure durable fixes.
Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.
Support org design, headcount planning, and hiring prioritization for engineering teams.
Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes
Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.
Support the head of engineering with administrative and org related activities
Milestone tracking - maintain methodology checklists and boundary agreements to ensure schedule adherence.
IP and vendor tracking - own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.
Drive cross-engineering outcomes through credibility, clarity, and follow-through - not hierarchy.

10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).
Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role.
Strong technical acumen - able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.
Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).
Proven ability to organize complex workflows and drive consistent follow-through.
High EQ and organizational awareness
can navigate tension and align diverse viewpoints.
Exceptional written/verbal communication, structured thinking, and execution discipline.
Prior experience in leading RTL2GDSII chip design is a huge plus.
What Success Looks Like
Engineering leadership spends more time on strategic and technical decisions, less on coordination.
Milestones hit with fewer escalations and clearer accountability.

Salary range is $216,000 to $300,000 depending on experience, level, and business need.

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.