Celerocommunicationsinc

Senior/Principal High-Speed Analog Layout Design Engineer

Irvine, CA or San Jose, CA · Principal

Sponsorship not specified$150k-$250kDetected 5 days ago

PythonCadenceControlsLeadershipCommunicationProblem SolvingMentoringOrganizational Skills

About the role

You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success.
This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.

Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits.

At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams

Exposure to optical or high-speed analog interfaces is a strong plus
Strong organizational skills with high attention to detail and follow-through
Ability to multi-task and prioritize in a fast-paced, dynamic environment
Proactive, eager-to-learn mindset with excellent problem-solving skills
The chance to play a foundational role at a high-growth semiconductor start-up
Exposure to a wide variety of cross functional teams
A collaborative, international team culture where ideas and initiative are valued
The opportunity to grow alongside Celero as we scale and shape the future of our industry

$150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems.

This listing is sourced directly from Celerocommunicationsinc's careers page and normalized into a canonical job model.