Cadence
Sr. Principle Design Engineer
AUSTIN · Senior
Sponsorship not specifiedDetected 7 days ago
Cadence
About the role
- Memory controller verification experience We're doing work that matters.
Responsibilities
- Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team - particularly with respect to our quality Metrics.
Requirements
- UVM based functional verification environment development is required.
Company info
- At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
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