Altera
Senior Debug Verification Engineer
San Jose, California, United States · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$6,796 more — $155,896 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $155,896 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification.
- Using system full application to verify performance and identify short falls.
Responsibilities
- Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
- Create testcase and testbench with UVM methodology
Requirements
- 8+ years of experience with complex ASIC designs and/or verification
- 8+ years of experience with SystemVerilog language
- 8+ years of experience on UVM verification methodology, and formal verification method
- 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
- Strong communication skills and the ability to work with a team spread across different geography sites
- Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
- Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
Nice to have
- Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
Skills
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,000 USD
Benefits
- Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.