Altera

Altera

Full Chip Timing Modeling and Integration Engineer

San Jose, California, United States · Senior

Sponsorship not specified$133k-$193kDetected 11 days ago
PythonMachine LearningFPGAVerilogElectrical Engineering

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61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

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About the role

  • Altera is seeking highly qualified candidates to join our Full Chip Timing team.
  • Success in this role requires the ability to work effectively both independently and as part of a team while meeting aggressive schedules.
  • The pay range below is for Bay Area California only.

Responsibilities

  • Develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.
  • Collaborate with cross-functional teams to define timing modeling strategies and solutions.
  • Generate high-level timing models and perform timing model integration and validation.
  • Perform hands-on full-chip timing analysis, including clocking and timing constraint development.
  • Work with Front-End and Back-End design teams to understand design architecture and implementation.
  • Analyze extraction issues, design margins, timing signoff requirements, and timing quality checks.
  • Debug and troubleshoot a wide variety of technical issues, including difficult and critical design issues, and proactively intervene to resolve them.
  • Drive continuous improvement, efficiently solve technical issues, and communicate technical trade-offs across cross-functional and multi-site teams.
  • Work independently and collaboratively to deliver high-quality results within aggressive project schedules.
  • You will collaborate with cross-functional teams to define timing modeling strategies and solutions, generate high-level timing models, and integrate and validate timing models.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of industry experience in SoC development.
  • 5+ years of industry experience working with advanced semiconductor process nodes.
  • 5+ years of industry experience with industry-standard timing formats and design constraints, including Liberty, Verilog, and Synopsys Design Constraints (SDC).
  • 5+ years of industry experience with Static Timing Analysis (STA), including correlating STA results with SPICE.
  • 5+ years of industry experience in timing modeling and library quality assurance (QA).
  • 5+ years of industry experience applying silicon modeling concepts, such as LVF and POCV.
  • We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
  • Applicants must be eligible for any required U.S. export authorizations.
  • 5+ years of industry experience writing Python and Tcl scripts for design automation.

Nice to have

  • 7+ years of relevant industry experience.
  • Experience with common modes of operation, including functional and Design-for-Test (DFT), for use in timing constraint review and management.
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:

Skills

  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $133,200 - $192,825 USD

Company info

  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers.
  • This is a fast-paced, dynamic environment where you will be part of a high-performance design team working toward next-generation FPGA products.
  • Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers.
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This listing is sourced directly from Altera's careers page and normalized into a canonical job model.