GlobalFoundries
Staff Engineer, Analog Design
Richardson, USA · Staff+
Sponsorship not specified$88k-$154kDetected 15 days ago
PythonMATLABCadenceElectrical EngineeringCommunicationCollaborationMentoring
About the role
- We are seeking a motivated Analog Design Engineer with 2–3 years of experience to contribute to the design and development of high-performance analog and mixed-signal IP. The ideal candidate will take ownership of block-level design while working closely with senior engineers on architecture and system-level integration.
- This role provides the opportunity to build upon strong fundamentals and expand into full design ownership, including silicon validation and cross-functional collaboration across global teams. Title: Staff Engineer, Analog Design (2–3 Years Experience)
Responsibilities
- Contribute to architecture discussions and design tradeoff analysis with senior team members
- Perform transistor-level schematic design, simulation, and verification using industry-standard EDA tools
- Work closely with layout engineers to ensure parasitic-aware design and performance closure
- Support and contribute to design reviews and verification planning
- Collaborate across disciplines including layout, verification, and SoC integration teams
- Generate clear documentation for design specifications, simulations, and validation results
- Mentorship of junior design/layout engineers in design best practices and effective collaboration
Requirements
- Bachelor's or master's degree in electrical engineering or related field
- 2-3 years of experience in analog or mixed-signal IC design
- Experience with transistor-level design and simulation in CMOS technologies
- Familiarity with industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.)
- Ability to run and analyze simulations across PVT and variability conditions
- Ability to work effectively in cross-functional, global teams
Nice to have
- Experience designing one or more analog blocks from spec to simulation (partial or full ownership)
- Exposure to silicon validation and lab debugging
- Familiarity with layout concepts and parasitic effects
- Experience with low-power design techniques
- Exposure to advanced nodes such as Bulk CMOS, FDSOI, or FinFET
- $88,000.00 - $154,000.00
- Requests for accommodation will be considered on a case-by-case basis.
- Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
Compensation
- Stability and compensation
Benefits
- Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs
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