Astera Labs Inc.
DFT Design Engineering Director
San Jose, California, United States · Director
Sponsorship not specifiedDetected 5 days ago
Machine LearningAccessibilityElectrical EngineeringLeadershipCommunicationCollaborationProblem Solving
About the role
- In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale.
- This role requires deep expertise in advanced packaging technologies including 2.5D and 3D integration, as our products leverage cutting-edge multi-die architectures.
- Multi-die test access and coordination through silicon interposers
Responsibilities
- Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging
- Lead and mentor a team of DFT engineers across multiple product development cycles
- Establish DFT best practices, methodologies, and flows for complex multi-billion transistor designs in advanced packaging configurations
- Develop DFT strategies for 2.5D/3D heterogeneous integration architectures:
Requirements
- 12+ years of experience in DFT engineering with complex SoC/ASIC products
- 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies
- 5+ years in technical leadership or management roles
- Proven track record of multiple successful tape-outs with high-volume production
- Technical Expertise
- Deep expertise in DFT methodologies and industry standards
- Strong understanding of ASIC design flow from RTL to GDS
- Excellent communication skills with ability to influence across organizations
Nice to have
- Experience with PCIe, CXL, or other high-speed serial protocols
- Background in SerDes architecture and testing
- Experience with HBM (High Bandwidth Memory) testing in 2.5D packages
- Knowledge of chiplet-based system architectures (UCIe, BoW, AIB)
- Familiarity with 3D stacking technologies (face-to-face, face-to-back bonding)
- Experience with wafer-level testing and probe strategies for advanced packages
- Understanding of PCIe/CXL link training, equalization, and state machines
- Prior experience in networking or switch product development
Skills
- Silicon interposer-based designs
- TSV technology and testing
- Chiplet architectures and die-to-die interfaces
- Known Good Die (KGD) test strategies
- CoWoS, EMIB, or similar advanced packaging platforms
- Understanding of JEDEC standards for multi-die testing (e.g., JESD229, JESD235)
- Experience with DFT EDA tools (Synopsys DFT Compiler, TetraMAX, DFTMAX, Mentor Tessent, etc.)
- Knowledge of high-speed SerDes architectures and testing requirements
- Familiarity with ATE platforms (Advantest, Teradyne) and test program development for advanced packages
- Understanding of production test economics and yield analysis for multi-die products
- Experience with IEEE 1149.1, IEEE 1687 (IJTAG), and IEEE 1838 (3D-DFT) standards
- Leadership & Communication
Compensation
- The base salary range is $230,000 USD – $265,000 USD.
Benefits
- Collaborate with design, verification, packaging, and product engineering teams to optimize test coverage and manufacturing cost
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