Celerocommunicationsinc
Senior/Principal Physical Design Engineer
San Jose, CA or Irvine, CA · Principal
Sponsorship not specified$150k-$250kDetected 6 days ago
PythonCadenceElectrical EngineeringLeadershipCommunication
About the role
- Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Responsibilities
- Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
- Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
- Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
- Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
- Partner with architects, logic designers, and analog design team for tapeout readiness.
Requirements
- 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
- Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus,, Tempus, Voltus, Pegasus, Calibre).
Nice to have
- San Jose, CA (preferred) or Irvine, CA (HQ)
- Core Responsibilities
Compensation
- $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
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