TPU SoC Integration Engineer, Cloud
Sunnyvale, CA, USA
Sponsorship not specified$163k-$236kDetected 1 day ago
PythonGCPMachine LearningElectrical EngineeringResearchCollaboration
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64Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
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About the role
- About the job In this role, you'll work to shape the future of AI/ML hardware acceleration.
- This role demands deep cross-domain collaboration, working closely with ASIC Packaging and Interposer teams to orchestrate complex interposer planning and implementation, alongside multi-die DFT connectivity and packaging routing.
Responsibilities
- Lead advanced SoC integration projects from concept to final delivery, managing project milestones, deliverables, and cross-functional schedules.
- Partner with ASIC teams on complex interposer and package design, and resolve multi-die physical design challenges leveraging 3DIO and domain partitioning expertise.
- Utilize software-based construction to seamlessly integrate SoC IPs and maintain complete ownership of the upper-level RTL hierarchy up to the package level.
- Collaborate closely with Verification and Emulation teams to resolve complex connectivity issues and optimize system compilation.
- Participate in critical layout design decisions and SoC-level sign-off activities to ensure robust, high-performance silicon delivery.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in ASIC design or RTL design.
- Experience with SoC design and integration.
- Experience with multi-chiplet SoC integration.
- Experience with SoC Design for Testing (DFT) planning.
- Experience scripting in Python or Perl or Tcl.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with SoC signoff-Logic Equivalence Check (LEC)/Lint/Unified Power Format (UPF)/CDC/Reset Domain Crossing (RDC) flows.
- Cross-functional experience with Design Verification (DV), Physical Design (PD), Clock Domain Crossing (CDC) and DFT teams.
- Experience designing and constructing ASIC Input/Output (IO) pad-rings.
- Knowledgeable in 3DIO methodology, voltage and clock domain partitioning.
- Knowledgeable in ASIC top-level Static Timing Analysis (STA) and clock planning.
- In this role, you'll work to shape the future of AI/ML hardware acceleration.
- The AI and Infrastructure team is redefining what's possible.
Compensation
- US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Company info
- We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
- Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
This listing is sourced directly from Google's careers page and normalized into a canonical job model.