Altera
Product Failure Analysis Engineer
San Jose, California, United States · Senior
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$16,593 more — $165,693 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $165,693 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Mechanical Engineers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Mechanical Engineers (17-2141) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- We are seeking an experienced semiconductor Failure Analysis Engineer responsible for debug and root cause analysis of yield, reliability and customer returns on FPGA's using advanced foundry process technologies.
- In this role, focus will be on non-destructive electrical fault isolation by debugging electrical test responses and circuit/layout analysis.
Responsibilities
- Collaborate with Product/Yield/Reliability Engineers to drive electrical verification, and fault isolation during product development, yield improvement and reliability risk assessments
- Support debug and fault isolation on customer returns
- Collaborate with physical failure analysis team on defect modes
- As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
- This role requires partnering with IC and Package design, Foundry Engineering, Product and manufacturing Engineering, and Reliability teams for driving systematic fault isolation and debug.
Requirements
- Bachelor's degree in Electrical Eng, Materials Science, Physics, Mechanical Engineering or a related field
- 8+ years of experience in semiconductor failure analysis
- 8+ years of experience with Layout & Design tools (Virtuoso, Avalon, SysNav, etc)
- 8+ years of experience with FA tools such as Laser Voltage Probing (LVP), Photo Emission EMMI, Optical Beam Induced Resistance Change (OBIRCH)
- 8+ years of experience with DFT and logic fault localization knowledge.
- 8+ years of experience driving investigations to root-cause and to drive yield/reliability improvements.
- Applicants must be eligible for any required U.S. export authorizations.
Nice to have
- 10+ years of experience in semiconductor failure analysis
- Understanding of FPGA architecture
- Experience with using Teradyne Ultraflex tester
- Semiconductor packaging failure analysis.
- Shift 1 (United States of America)
- San Jose, California, United States
- Posting Statement:
Skills
- About Altera
- Proficient in independently using Emission microscopes, Laser Voltage Probing and OBIRCH tools
- Experienced with layout, schematic and design analysis tools
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,925 USD
Company info
- About the Role We are seeking an experienced semiconductor Failure Analysis Engineer responsible for debug and root cause analysis of yield, reliability and customer returns on FPGA's using advanced foundry process technologies.
- We also offer incentive opportunities that reward employees based on individual and company performance.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.