Densityai

Densityai

Design for Test (DFT) Engineer

Mountain View, California, United States

Work authorization required$300k-$350kDetected 21 days ago
PythonRecruitingVerilogElectrical Engineering

About the role

  • This is a ground-floor role on a leading-edge multi-die package.

Responsibilities

  • Help build out and advance the DFT flow-insertion, pattern generation, verification, and signoff-integrated into the broader RTL-to-GDSII methodology
  • Architect and implement test access for our multi-die package-post-package scan-chain access, known-good-die (KGD) sorting and screening, die-to-die (D2D) interconnect test, and a package-level test-access architecture designed in from the start rather than retrofitted
  • Implement DFT structures across the full range: scan (stuck-at, transition/at-speed), compression, boundary scan (JTAG/IEEE 1149.x), and IEEE 1500 core wrapping
  • Implement and verify Memory BIST, with particular emphasis on external MBIST controllers and shared/centralized BIST architectures serving distributed memory instances
  • Perform DFT verification: scan chain integrity, pattern verification, and gate-level simulation (with SDF/timing) across all test modes
  • Support silicon bring-up, debug, diagnosis, and yield/failure analysis, correlating ATE results back to design
  • Collaborate with physical design on scan stitching, test point insertion, timing, and power-aware test (DFT interaction with power domains/UPF)
  • Document methodology and continuously automate and improve the flow
  • 7+ years of hands-on DFT engineering on complex digital SoC/ASIC designs

Nice to have

  • Deep Siemens Tessent expertise - Scan & ATPG (TestKompress), MemoryBIST (incl. external/shared MBIST), BoundaryScan/IJTAG (SSN a plus)
  • Low-power DFT (UPF/CPF, power-aware ATPG, retention/isolation test) (preferred)

Compensation

  • Final offers depend on level, location, and skills relevant to the role.
  • DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT.
  • Work authorization is required at start; we provide immigration support to secure or transfer status.
  • Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR).
  • We may discuss licensing or scope adjustments during the interview.
  • Visa Sponsorship

Benefits

  • Drive ATPG, fault simulation, coverage closure, and pattern conversion/porting to the ATE environment (STIL/WGL)
  • Help define and review DFT specifications, test access architecture, and test budgets (pin count, test time, coverage targets)
  • equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.

Company info

  • What we're looking for

Equal opportunity

  • DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
  • Full compensation packages are based on candidate experience and relevant certifications.
  • California pay range
  • $300,000 - $350,000 USD

Visa & Work Authorization

  • DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT.
  • Work authorization is required at start; we provide immigration support to secure or transfer status.
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This listing is sourced directly from Densityai's careers page and normalized into a canonical job model.