Astera Labs Inc.

Technical Lead Physical Design Engineer

Toronto, Ontario, Canada

Sponsorship not specifiedDetected 5 days ago

PythonCadenceVerilogElectrical EngineeringCollaboration

About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
This role is fully on-site and in-person.
The base salary range is $140,000 CAD - $180,000.00 CAD.

Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.
Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.
Define and manage I/O timing budgets across hierarchical designs.
Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.

≥5 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
Ability to work independently with strong prioritization and a professional, customer-focused mindset.
Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
Experience working with IP vendors for both RTL and hard-macro integration.

Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.
Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.
Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.