Nuvacore
CPU Architecture Verification Engineer
Austin, TX · Senior
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$12,360 more — $152,360 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $152,360 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · Austin-Round Rock-San Marcos, TX. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
- Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
- Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
Responsibilities
- Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads.
- Drive the verification scope, strategy, and test plans for architectural correctness - the CPU's behavior and architectural state versus the specification and a golden reference model.
- Build, maintain, and scale robust verification environments - including co-simulation against the golden reference model - that compare architectural state end to end.
- Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.
- Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness - the CPU's behavior and architectural state versus the specification and a golden reference model.
- Environment Setup: Build, maintain, and scale robust verification environments - including co-simulation against the golden reference model - that compare architectural state end to end.
- Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.
Requirements
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
- Strong knowledge of CPU architecture and micro-architecture - the instruction set, architectural state, exceptions, and privilege model - with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
Nice to have
- Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python
Compensation
- $140k-$250k
Company info
- We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove that the Nuvacore CPU is architecturally correct.
- As part of the design verification (DV) team, you will help drive architectural verification - checking the CPU's behavior and architectural state against the architecture specification and a golden reference model - building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.
This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.