Altera
AI Architect, Agentic AI for Chip Design & EDA
San Jose, California, United States · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$11,874 more — $221,374 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $221,374 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Software Developers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Software Developers (15-1252) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Advance domain-specific Large Language Models (LLMs) and foundation models tailored for semiconductor workflows.
- Leverage silicon learning and manufacturing data to establish closed-loop optimization methodologies.
Responsibilities
- AI-Powered Chip Design & EDA Innovation
- Lead the strategy, architecture, and development of AI-driven solutions for semiconductor design and optimization.
- Develop and deploy Agentic AI systems that automate complex engineering workflows across RTL, synthesis, physical design, signoff, DRC, power planning, validation, and 3D-IC design.
- Build intelligent multi-agent platforms capable of autonomous decision-making, design exploration, and flow optimization.
- Drive applications leveraging Retrieval Augmented Generation (RAG), AI copilots, code generation, and autonomous engineering agents.
- Semiconductor Design Optimization
- Lead AI initiatives that improve chip Power, Performance, Area (PPA), manufacturability, reliability, and silicon yield.
- Partner with product and engineering teams to integrate AI capabilities into commercial EDA platforms.
- Architect enterprise-scale AI and analytics platforms supporting EDA workloads and semiconductor design data.
- Develop scalable software systems utilizing Python, C/C++, databases, cloud infrastructure, big data technologies, and distributed computing frameworks.
Requirements
- 12+ years of semiconductor industry experience with expertise spanning multiple phases of the silicon lifecycle.
- Proven technical leadership experience leading large-scale engineering initiatives.
- Strong understanding of semiconductor manufacturing, yield analysis, DTCO, or design enablement.
- Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related technical field.
- Deep understanding of digital IC design, RTL development, synthesis, physical implementation, timing closure, verification, and signoff methodologies.
- Strong expertise in AI/ML technologies, including Generative AI, LLMs, reinforcement learning, graph neural networks, and predictive modeling.
- Advanced programming skills in Python and one or more of C/C++, Java, or similar languages.
- Experience building enterprise software, AI platforms, analytics applications, or automation systems.
Nice to have
- Hands-on expertise with leading EDA tools and workflows from Cadence, Synopsys, Siemens EDA, or equivalent platforms.
- Expertise with cloud computing, distributed systems, Spark, data engineering, and large-scale AI infrastructure.
- Knowledge of 3D-IC, advanced packaging, silicon photonics, advanced process technologies, or foundry operations.
- Track record of patents, publications, conference presentations, or industry-recognized technical contributions.
- Experience leading global, multidisciplinary engineering teams.
- What Success Looks Like
- Creating scalable platforms that bridge semiconductor engineering, AI, and data science.
- Influencing the future direction of AI-enabled EDA and semiconductor innovation.
Compensation
- The pay range below is for Bay Area California only.
Benefits
- Develop machine learning and reinforcement learning solutions for automated design space exploration and optimization.
- Apply Graph Neural Networks (GNNs), deep learning, and predictive analytics to accelerate semiconductor design convergence.
- Drive Design Technology Co-Optimization (DTCO) initiatives linking design, process development, manufacturing, and yield learning.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.