Baidu
Design Verification Engineer
Sunnyvale,CA
Sponsorship not specifiedDetected 85 days ago
PythonVerilogSystems EngineeringCommunicationProblem Solving
About the role
- The successful candidate will be a motivated self-starter who will thrive in this highly technical environment.
- You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
- We watch out for each other and go after big goals together as a team. #LI-DNI
Requirements
- Minimum 5 years of experience of UVM based verification on a significantly complex project.
- Advanced knowledge of System Verilog and the UVM methodology.
- Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
- Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
- Good practice of one scripting language (Perl, Python, Tcl) no preference.
- SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
- Familiar with C/C++.
- Formal Verification (Model Checking, Equivalence Checking).
- Excellent communication skills in both English and Chinese.
- Culture Fit:
- Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
- Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
This listing is sourced directly from Baidu's careers page and normalized into a canonical job model.