Astera Labs Inc.
Principal Design Verification Engineer- SerDes/PHY IP
San Jose, California, United States · Principal
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$11,899 more — $218,899 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $218,899 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story.
Responsibilities
- Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
- Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
- Model and validate channel behavior, link training state machines, and analog handoff scenarios
- Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
- Expert-level proficiency in SystemVerilog and UVM
- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
- Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
- Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
- Scripting proficiency in Python or Perl for verification automation and regression management
Skills
- Verification Architecture & Strategy
- Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
- Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
- Execution & Coverage Closure
- Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios
- Physical Layer & Protocol Verification
- Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards
- Cross-Functional Leadership
- Mentor junior DV engineers and set technical direction across the verification team
- Contribute to verification IP reuse strategy and tooling improvements across product lines
Compensation
- Salary range is $207,000 to $230,000 depending on experience, level, and business need.
Benefits
- Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.