Altera

Altera

Product Physical Failure Analysis Engineer

San Jose, California, United States · Senior

Sponsorship not specified$149k-$216kDetected 15 days ago
Product ManagementSEMFPGAMechanical DesignElectrical EngineeringMicroscopy

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odds of building a lasting career here

61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

H-1B wage level

the lottery is wage-weighted — each level is one more entry

Level II · 2×
Level I$117,9981 entry
Level II$141,8352 entries
Level III$165,6933 entries
Level IV$189,5304 entries

$16,593 more$165,693 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.

Based on the DOL prevailing wage for this occupation and worksite, a base salary of $165,693 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Mechanical Engineers" for prevailing-wage purposes.

DOL prevailing wage, 2026-27 wage year · Mechanical Engineers (17-2141) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.

Employer immigration record

from this employer's Department of Labor filings

Green-card intent detected

Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file

Files H-1B transfers

13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
  • We are seeking an experienced semiconductor Physical Failure Analysis Engineer responsible for root cause identification on yield, reliability and customer returns.

Responsibilities

  • Collaborate with Product/Yield/Reliability Engineers to drive fault isolation during product development, yield improvement and reliability risk assessments
  • Support physical failure analysis and root cause determination of semiconductor device failures
  • Collaborate with Fault isolation engineers or Independently interpret Emission microscopes, Laser Voltage Probing and OBIRCH data and to define physical failure analysis process
  • Develop reports and communicate findings to the responsible engineers on a regular basis
  • As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

Requirements

  • BS degree in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, or a related field
  • 8+ years of experience in semiconductor failure analysis
  • 8+ years of experience with Layout & Design tools (Virtuoso, Avalon, SysNav, etc.)
  • 8+ years of experience driving investigations to root cause and driving yield/reliability improvements
  • Applicants must be eligible for any required U.S. export authorizations.
  • 8+ years of experience independently implementing failure analysis using die milling/thinning, Focused Ion Beam milling for layer-by-layer deprocessing of silicon die, Scanning Electron Microscopy, and Energy Dispersive X-ray Spectroscopy

Nice to have

  • Understanding of FPGA architecture
  • Experience with using Teradyne Ultraflex tester
  • Experience in semiconductor packaging failure analysis.

Skills

  • About Altera
  • Independently define, and execute physical failure analysis tools such as SEM, FIB and EDX
  • Experienced with layout, schematic and design analysis tools
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $149,100 - $215,925 USD

Company info

  • About the Role We are seeking an experienced semiconductor Physical Failure Analysis Engineer responsible for root cause identification on yield, reliability and customer returns.
  • We also offer incentive opportunities that reward employees based on individual and company performance.

This listing is sourced directly from Altera's careers page and normalized into a canonical job model.