Cerebras Systems
FPGA Engineer
Sunnyvale, CA · Senior
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About the role
- ii) a large programmable switching fabric
- and iii) Serial IO communication with the Cerebras WSE via a proprietary protocol.
Responsibilities
- Lead full chassis-to-wafer IO architecture and design
- Improve current RTL, implement next-gen FPGA design, define future IO architectures
- Optimize bandwidth/latency over FPGA datapath and all IO interfaces
- Drive network performance debug of large AI clusters
- Lead cross-functional technical projects spanning multiple teams and integrating diverse software and hardware components to deliver an improved network IO solution.
Requirements
- 5+ years industry experience generating production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience,
- Proficiency in Verilog development in Git based repo
- Knowledge of network switch environments or willingness to learn (Arista, Juniper, etc.).
- Highly productive with FPGA placement & routing, timing closure, simulation, debug, and other FPGA tools/workflows
- Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark
- AI-augmented development environment
Skills
- Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups.
Company info
- Build a breakthrough AI platform beyond the constraints of the GPU.
- Publish and open source their cutting-edge AI research.
- Work on one of the fastest AI supercomputers in the world.
- Enjoy job stability with startup vitality.
- Our simple, non-corporate work culture that respects individual beliefs.
This listing is sourced directly from Cerebras Systems's careers page and normalized into a canonical job model.