Altera

Altera

Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization

San Jose, California, United States · Principal

Sponsorship not specified$266k-$392kDetected 12 days ago
C++Data StructuresAlgorithmsFPGAElectrical EngineeringLeadershipMentoring

About the role

  • This role will provide technical leadership across the Quartus compilation flow, with a particular emphasis on Static Timing Analysis (STA), timing closure, timing modeling, optimization algorithms, and scalable compiler infrastructure.
  • The successful candidate will work closely with architecture, synthesis, fitting, routing, and timing teams to improve compiler quality of results (QoR), runtime, scalability, and signoff correlation for next-generation FPGA devices.
  • The pay range below is for Bay Area California only.

Responsibilities

  • Define and drive the technical roadmap for timing analysis, timing modeling, and timing optimization within the Quartus FPGA Compiler.
  • Lead the design and implementation of advanced timing engines supporting FPGA compilation, placement, routing, and timing closure.
  • Develop methodologies to improve timing convergence across the Quartus RTL-to-bitstream flow.
  • Partner with architecture and compiler teams to enable best-in-class timing QoR and signoff correlation.
  • Architect and develop next-generation STA capabilities, including graph-based and path-based timing analysis.
  • Develop timing modeling methodologies that accurately correlate Quartus results with silicon behavior and signoff requirements.
  • Drive innovations in delay modeling, clock modeling, timing abstraction, and hierarchical timing analysis.
  • Partner with FPGA architecture teams to ensure accurate representation of device resources and timing characteristics.
  • Design scalable data structures and algorithms for timing analysis and optimization.
  • Drive architectural improvements that enable efficient handling of large, complex FPGA designs.

Requirements

  • 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains.
  • Deep expertise in:
  • Strong understanding of:
  • Extensive software development experience in C++ and large-scale optimization systems.
  • MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or related field.

Nice to have

  • Prior experience with the Quartus compiler, Timing Analyzer, Fitter, Routing, or related FPGA implementation technologies.
  • Expertise in one or more of the following:
  • Path-based timing optimization
  • Clock-Reconvergence Pessimism Removal (CRPR)
  • Latch-based timing analysis
  • Incremental optimization frameworks
  • Timing-driven placement and routing
  • Variation-aware analysis techniques

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
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