Broadcom

Lead ASIC Design Engineer

USA-California-San Jose-1320 Ridder Park Drive

Work authorization required$144k-$230kDetected 32 days ago

PythonCode ReviewCadenceVerilogElectrical EngineeringLeadershipCommunicationMentoring

About the role

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In this high-impact role, you will be the primary technical anchor responsible for the top-level architecture, microarchitecture, and full chip integration.
The company follows all applicable laws for Paid Family Leave and other leaves of absence.

You will guide a cross-disciplinary team spanning analog design, physical design, and verification, owning the design outcome end-to-end from early product definition to a successful foundry tape-out.
Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
Drive top-level chip timing constraints ( SDC ), define the Clock Domain Crossing ( CDC ) strategy, and establish block-level timing budgets for the PD team.
Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis ( STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.
12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
All subject to relevant plan documents and award agreements.

RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.
Work Authorization: Must have legal authorization to work in the US.
Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).
Proficiency in scripting ( Python, Tcl, Perl ) to automate and streamline front-end design flows.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).

The annual base salary range for this position is $143,800 - $230,000.
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
All subject to relevant plan documents and award agreements.

Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
Compensation and Benefits

Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.
Technical Execution Responsibilities
We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects.

This listing is sourced directly from Broadcom's careers page and normalized into a canonical job model.