credosemi
Senior Physical Design Engineer
San Jose, California · Senior
Sponsorship not specified$140k-$170kDetected 10 days ago
CadenceCollaboration
About the role
- This role involves close collaboration with the local frontend team and PD/integration teams in China and Taiwan to ensure successful tapeouts.
Responsibilities
- Lead and drive top-level, IP, and block-level physical implementation from RTL to GDSII.
- Establish and maintain physical design methodologies, flow automation, chip floorplanning, power/clock distribution, chip assembly, P&R, and timing closure.
- Perform static timing analysis, power and noise analysis, and physical verification.
- Collaborate closely with frontend and integration teams to ensure successful tapeouts.
- As a Senior Physical Design Engineer, you will manage all aspects of physical design and implementation for Credo SoC designs.
Requirements
- Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure.
- Experience with 5nm and lower technology nodes.
- Strong proficiency with EDA tools such as Cadence Innovus and Synopsys Fusipn Compiler.
Nice to have
- Familiarity with DRC, Antenna, LVS, ERC tools like Calibre.
- Credo is an Equal Opportunity Employer.
Skills
- Credo is engineering the future of high-speed connectivity for the AI-driven world.
Compensation
- The base salary range for this position is $140,000 – $170,000 a year.
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