Altera

Altera

Custom Analog Design Automation Lead

San Jose, California, United States · Senior

Sponsorship not specified$232k-$341kDetected 28 days ago
PythonMachine LearningCadenceElectrical EngineeringLeadershipCommunication

Stay score

odds of building a lasting career here

61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

H-1B wage level

the lottery is wage-weighted — each level is one more entry

Level IV · 4×
Level I$124,4051 entry
Level II$155,8962 entries
Level III$187,4083 entries
Level IV$218,8994 entries

This range already reaches Level IV — the maximum four lottery entries.

DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.

Employer immigration record

from this employer's Department of Labor filings

Files H-1B transfers

13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • Establish metrics to track productivity, quality, and adoption of automation and AI-assisted flows, and report progress to engineering leadership.
  • The pay range below is for Bay Area California only.

Responsibilities

  • Define and drive the technical strategy and roadmap for analog design automation and AI-assisted productivity tools.
  • Develop, deploy, and maintain automation flows that span custom-analog design tasks, from schematic and layout through verification and signoff.
  • Identify opportunities to apply AI/ML techniques to analog design problems (e.g., sizing, layout assistance, verification triage) and lead proof-of-concept through production deployment.
  • Own the reuse and hardening strategy for analog IP and automation flows, ensuring methodologies are robust, well-documented, and portable across projects.
  • Partner with design, CAD, and methodology teams to roll out automation and AI-assisted capabilities consistently across fabric, SerDes, and IO design groups.
  • Mentor and provide technical direction to design and automation engineers adopting new flows and methodologies.
  • Stay current with emerging EDA, automation, and AI/ML technologies relevant to custom-analog design, and evaluate them for adoption.
  • Analog design automation spanning fabric, SerDes, and IO design domains.
  • Reuse and hardening strategy for analog design IP, flows, and methodologies.
  • Cross-team methodology deployment, influencing practices across multiple design groups rather than a single project.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 12+ years of experience in custom-analog circuit design and/or analog design automation, combined with hands-on experience in design automation and/or AI-assisted methodologies.
  • We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
  • Applicants must be eligible for any required U.S. export authorizations.
  • Demonstrated ability to develop and deploy design automation methodology across multiple teams, not just within a single project.
  • Working knowledge of analog/mixed-signal design flows (schematic capture, layout, extraction, verification) and the EDA toolchains that support them - Cadence Virtuoso Studio, Maestro/ADE, Spectre, Quantus QRC, Voltus-XFi/EMIR, Synopsys HSPICE/PrimeSim, or equivalent.
  • Expert-level scripting and automation ability (Cadence SKILL, Python, Tcl, shell), sufficient to build and maintain production automation rather than extend what already exists.
  • Demonstrated application of AI/ML to design or verification workflows, taken past proof-of-concept into production use by engineers other than the author.
  • Direct experience working with foundry PDKs and EDA vendors to debug, characterize, and qualify tool behaviour at [CONFIRM
  • Strong communication and leadership skills, with the ability to influence design practices across fabric, SerDes, and IO teams.

Nice to have

  • Prior experience leading a Center of Excellence (CoE) or cross-functional capability team.
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:

Skills

  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $231,500 - $341,075 USD

Company info

  • We also offer incentive opportunities that reward employees based on individual and company performance.

This listing is sourced directly from Altera's careers page and normalized into a canonical job model.