Astera Labs Inc.
Principal Physical Design Engineer
San Jose, California, United States · Principal
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$2,408 more — $187,408 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,408 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Astera Labs is redefining the connectivity fabric that powers rack-scale AI infrastructure.
- This is a hands-on technical leadership role.
Responsibilities
- Own the full RTL2GDS flow on advanced process nodes - synthesis, floorplan, placement, CTS, routing, and signoff - across Astera's connectivity product portfolio
- Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs
- Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab
- Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff
- Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure
- Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies
- Establish and evolve physical design methodology, scripts, and flows across the team
- Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below)
- Deep expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime)
- Proficiency in Tcl/Python scripting for flow automation
- Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production
Nice to have
- MS in Electrical Engineering or Computer Engineering
- Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs
- Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates)
- Experience mentoring senior engineers and driving methodology adoption across teams
Skills
- End-to-End RTL2GDS Ownership
- Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets
- Timing, Power & Signoff
- Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around
- Technical Leadership & Cross-Functional Partnership
Compensation
- Salary range is $185,000 to $230,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.