Altera
DDR Memory Interface System Validation Lead Engineer
San Jose, California, United States
Sponsorship not specified$149k-$215kDetected 30 days ago
FPGAElectrical EngineeringLoad Testing
About the role
- We are seeking a highly motivated and experienced DDR5 / LPDDR5 Memory Validation Engineer to join our Silicon and Platform Validation organization.
- This position offers the opportunity to work hands-on with cutting-edge memory technologies, advanced PHY architectures, and high-speed validation infrastructure while influencing future FPGA platform capabilities and validation methodologies.
Responsibilities
- Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs.
- Create, define, and develop comprehensive system-level validation environments and test suites for advanced memory interface validation.
- Perform pre-silicon and post-silicon functional and electrical validation of DDR5 and LPDDR5 controllers, PHYs, and associated high-speed interfaces.
- Develop and execute validation plans covering:
- Perform timing characterization, compliance checks, interoperability testing, and performance validation according to JEDEC specifications.
- Collaborate with hardware board design teams on high-speed memory channel implementation, including:
- Review schematics, layouts, and board design guidelines for DDR5 and LPDDR5 implementations.
- Develop, standardize, and maintain validation methodologies, automation frameworks, and measurement flows to improve validation scalability and efficiency.
- Partner with silicon design, package, board, firmware, and software teams to drive root-cause analysis and issue resolution.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.
- Minimum of 8+ years of industry experience in memory subsystem validation, silicon validation, or high-speed interface validation.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
Skills
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,000 USD
Benefits
- Collaborate with pre-silicon validation teams to improve post-silicon coverage and future debug capabilities.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.