Astera Labs Inc.
Firmware Engineer Tech Lead
San Jose, California, United States
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$27,075 more — $187,075 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,075 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Software Developers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Software Developers (15-1252) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.
Requirements
- Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
- Required Experience
- Experience working on PCIe-Express (Gen-3 and above) protocol, including working with analyzers and exercisers to debug protocol issues.
- High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
- Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces.
- Experience with PAM4 SerDes with working knowledge of Tx/Rx equalization, adaptation, CDR and SerDes link budgets.
- Hands-on experience with PCIe devices in Server, Storage, and/or Networking equipment.
Nice to have
- Strong academic and technical background in electrical engineering.
- At a minimum, a Bachelor's in EE or Computer Science is required, and a Master's is preferred.
- High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
- Preferred Experience
Skills
- Labs (NASDAQ:
- ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Discover more at www.asteralabs.com.
Compensation
- Base salary range is $160,000 to $200,000 depending on experience, level, and business need.
Company info
- The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs' SoC and systems products.
Visa & Work Authorization
- Authorized to work in the US and start immediately.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.