Winmaxsystemscorporation
IC Design Verification Engineer
San Jose, CA, United States · Full-time
Sponsorship not specifiedDetected 3353 days ago
PythonCadenceVerilogTCP/IP
About the role
- In this role you will be architecting and implementing the infrastructure including test-benches, APIs, golden reference models, 802.11 specific protocol layer generators and checkers.
- You will also be responsible for establishing metrics and implementing tests for functional correctness, coverage, and performance characterization.
Requirements
- Typically requires a BSCS/BSEE degree and 8 years of related experience, an MSCS/MSEE degree and 6 years of related experience
- Knowledge of wired or wireless networking protocols is desirable
Nice to have
- SystemVerilog/OVM/UVM is required and OO programming experience is a plus
- Knowledge of assertion based (SVA, PSL based) methodologies - formal and simulation - is necessary
- Working knowledge of scripting in Perl, Python, Tcl, and C
- Experience with logic simulators and debug tools from Cadence, Synopsys, and Mentor
- Capability to learn new skills or technologies as needed and be self-motivated
- All your information will be kept confidential according to EEO guidelines.
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